Multi-core processors may experience greater impact from cache misses and cache busy events. A number of factors may result in increased cache misses on multi-core processors, such as linear superscalar optimization, where instructions may be loaded for the next execution step during the previous execution step, and simultaneous multi-threading, in which processes may be swapped during execution delays. Tracking processes in multi-core processors and moving processes between cores may further impact cache capabilities. A multicore chip may have both a private per-core Level 1 (L1) cache and a chip-wide shared Level 2 (L2) cache and cache penalties may be most acute when multiple cores seek access to the L2 cache.